publications

2026

1. 

   A Unified Platform to Evaluate STDP Learning Rule and Synapse Model Using Pattern Recognition in a Spiking Neural Network

   Jaskirat Singh Maskeen and Sandip Lashkare

   In Artificial Neural Networks and Machine Learning – ICANN 2025, 2026

   Abs DOI

   We develop a unified platform to evaluate Ideal, Linear, and Non-linear }}\backslashtext {Pr}_{0.7}\backslashtext {Ca}_{0.3}\backslashtext {MnO}_{3}}}Pr0.7Ca0.3MnO3memristor-based synapse models, each getting progressively closer to hardware realism, alongside four STDP learning rules in a two-layer SNN with LIF neurons and adaptive thresholds for five-class MNIST classification. On MNIST with small train set and large test set, our two-layer SNN with ideal, 25-state, and 12-state non-linear memristor synapses achieves 92.73 %, 91.07 %, and 80 % accuracy, respectively, while converging faster and using fewer parameters than comparable ANN/CNN baselines.

2. 

   Asynchronous real-time learning in Spiking Neural Network using 3-terminal Resistance Random Access Memory

   Harshvardhan Singh, Nirmal Solanki, Jaskirat Singh Maskeen, and 3 more authors

   Microelectronic Engineering, 2026

   Abs DOI

   Spiking Neural Networks (SNNs) inspired by the human brain are promising alternative to solve real-life complex problems, such as pattern recognition at low energy consumption. A key approach to implementing SNNs involves using a Resistance Random Access Memory (RRAM) crossbar array to simulate synaptic weights, which can have multi-step resistance states suitable for processing analog signals. However, a major hurdle with traditional 2-terminal RRAMs is the “read–write dilemma”: the low voltage needed for a non-destructive read operation conflicts with the high voltage required for a write operation, making simultaneous, real-time learning challenging. Current solutions to this problem, such as time or frequency division multiplexing and separate read/write arrays, increase the circuit’s complexity, size, or operation time. This paper proposes a novel solution using a recently developed 3-terminal (3T) Pr0.7Ca0.3MnO3 (PCMO) RRAM. By using two terminals for writing and a third, dedicated decoupled terminal for reading, this architecture allows for simultaneous and asynchronous read and write operations. This approach resolves the read–write conflict inherent in 2-terminal designs, enabling real-time learning in SNNs without significant increase in circuit overhead and learning time.

2025

1. 

   HZO based FeFET with Sub 2-nm EOT Gate Stack as Synapse for Spiking Neural Network

   Jaskirat Singh Maskeen, Apu Das, Gautham Kumar, and 9 more authors

   In 2025 IEEE 7th International Conference on Emerging Electronics (ICEE), Dec 2025

   Abs DOI

   Ferroelectric FET (FeFET) synapses based on HZO with a sub-2 nm EOT gate stack promise dense, low-power neuromorphic hardware. Yet, their system efficacy is tightly coupled to the particulars of device-level electrical characterization. In this work, we establish a quantitative device-to-algorithm link by evaluating how standard measurement controls such as program/erase pulse amplitude, pulse duration, and cycling endurance, shape the FeFET memory window, weight uniformity and, in turn, impact spiking neural network (SNN) performance. Using experimentally measured transfer characteristics and pulse responses, we show that reductions in memory window and increased update non-uniformity induced by sub-optimal pulse conditions directly constrain the attainable weight range and weight-change linearity, degrading accuracy and stability during SNN training/inference. We map the feasible operating envelope that jointly maximizes memory window, monotonicity, and endurance, and translate it into actionable pulse-engineering guidelines (amplitude-width co-tuning and endurance-aware programming schedules) for synaptic updates. By closing the loop from metrology to application, this study provides a systematic methodology to co-optimize FeFET electrical characterization and SNN performance, offering practical screening criteria for wafer-level device selection and a pathway to reproducible, deployment-grade neuromorphic systems with sub-2 nm-stack FeFET synapses.